This invention relates in general to voltage converter circuits and more particularly to a supply voltage converter circuit for use in reduced geometry high-density semiconductor memory devices.
Recent semiconductor memory devices frequently have metal-oxide-semiconductor (MOS) transistors having an effective channel length short as 1 .mu.m or even shorter, to achieve high-speed operation and increased integrity of circuit arrangement. Due to hot electrons, resulting from such a size reduction in MOS transistors, reliability of MOS transistors generally degrade. To prevent the reliability of MOS transistors from degrading due to channel punch-through, it is necessary to drive these devices with an internal source voltage of less than 5 volts, of which is in current use for a standard source voltage (or reference voltage) or an external source supply voltage. In general, MOS transistors of short channel length are used in memory array circuit of a dynamic random access memory (DRAM) devices comprising bit lines, sense amplifiers, bit-line precharging circuits and memory cells therein, and also in its peripheral devices. In DRAM devices, when the bit lines are precharged with the memory array circuit, a large instantaneous current flows into the memory array circuit. Hence, a variation of source voltage resulting from such a current affects operation of the peripheral and other circuits. To solve these problems, there has generally been employed a system having, on a same chip the source voltage converting circuit for memory array circuits and a source voltage converting circuit for peripheral circuits, independent of each other. However, an output buffer is driven with an external source voltage (usually 5 volts), to ensure its TTL (transistor-transistor-logic) level of output. Known art relating to such a source-supply-voltage converting circuit was disclosed in IEEE Journal of Solid State, June 1987 issue, VOL. SC-22, NO. 3, PP 437-440.
Referring to the known art of this treatise, the two source-supply-voltage converting circuits for a memory array circuit each and a peripheral circuit, each have the same construction as each other. Referring to FIG. 1 of the prior art, the source-supply-voltage converting circuit of the memory array contains a reference voltage generator 10, for generating a fixed reference voltage from an external supply voltage V1, a power MOS transistor Q1, for providing an internal supply voltage V2, equal to that is the reference voltage, to the memory array circuit, and a current-mirror differential amplifier 12 for comparing the reference voltage with the internal supply voltage and controlling conductance of the power MOS transistor Q1 so as to make the reference voltage identical to the internal supply voltage. The differential amplifier includes a load transistor Q3 activated by a pulse .phi. upon precharging of the bit lines, and another load transistor Q2 coupled with the load transistor Q3 in parallel and kept in a normally ON state. Since current flow through the power MOS transistor Q1 is subject to an abrupt change upon precharging the bit lines, a prompt response can be achieved by increasing the current flow through the differential amplifier 12.
Hence, the size (ratio of channel width as its length) of the load transistor Q3 is larger than that of the other load transistor Q2. Also, since the load transistor Q2 always keeps its conduction state (turn-ON state), its size should be made as small as possible in order to minimize its current consumption at a stand-by state. However, to improve gain of the differential amplifier 12, transistors Q4-Q7 within the differential amplifier are required to operate in their saturation regions. Therefore, since the transistors Q4-Q7 are designed to be large in size, taking into account the size of load transistor Q3 made turn-ON upon charging the bit lines consuming large current, the size of load transistor Q2 can not be freely made smaller irrespectively the size of transistors Q4-Q7. Hence, there may arise a problem that current consumption through the load transistor Q2 becomes large in its stand-by state. Furthermore, reducing the size of load transistor Q2 results in slow-down of operational speed in its stand-by state.